Generating a design for a field programmable gate array (FPGA) can be complex process primarily due to the large number of circuitry elements in the design and aggressive timing requirements. A substantial amount of the design process is spent on closing the timing of the designs—i.e., ensuring the circuitry meets the timing requirements. As the number of design blocks and corresponding connections in a design increase so does congestion in the FPGA programmable logic which increases the amount of time needed by backend router tools to identify routes that satisfy the timing requirements.